This invention relates to a semiconductor device having a chip and a sealing cap for sealing the chip.
A conventional semiconductor device of the type described is disclosed in Japanese Unexamined Patent Prepublication (Kokai) No. 192125/1989. The conventional semiconductor device comprises a substrate, a chip, and a sealing cap. A plurality of conductor lines are formed on a principal surface of the substrate. The chip has an integrated circuit, a first chip surface, and a second chip surface. The chip further has a plurality of bumps and conductor films. The conductor films cover the bumps and are connected to the integrated circuit. The conductor films are protruded from the first chip surface.
The sealing cap has an under end surface, an internal wall surface, and an internal upper surface. The internal wall and the internal upper surfaces define a hole which receives the chip. The sealing cap has an elastic film with the elastic film glued to the internal upper surface. The under end surface is glued to the principal surface by a sealing adhesive mass with the chip pushed towards the conductor lines by the elastic film. The conductor films are brought into contact with a pressure force by an elastic force of the elastic film.
The substrate has a primary coefficient of thermal expansion. The sealing cap has a secondary coefficient of thermal expansion. When the primary coefficient of thermal expansion is extremely different from the secondary coefficient of thermal expansion, shearing stresses are caused to occur in the bumps and the conductor films by heating and cooling the chip, the substrate, and the sealing cap. Consequently, the semiconductor device is easily destroyed by the shearing stress.
Another semiconductor device is disclosed in Japanese Unexamined Patent Prepublication (Kokai) No. 355937/1992. The conventional semiconductor device comprises the substrate, the chip, and the sealing cap. The conductor lines are formed on the principal surface. A plurality of conductor bumps are formed on the conductor lines. The chip has the integrated circuit, the first chip surface, and the second chip surface. The chip further has a plurality of conductor pads connected to the integrated circuit. The conductor pads are protruded from the first chip surface.
An adhesive layer is formed on the second chip surface. The sealing adhesion mass is formed on the principal surface. The sealing cap has the under end surface, the internal wall surface, and the internal upper surface. The internal wall and the internal upper surfaces define the hole which receives the chip with the internal upper surface glued to the second chip surface by the adhesive layer and with the under end surface glued to the principal surface by the sealing adhesive mass. The conductor pads are brought into contact with the conductor bumps by elastic forces of the conductor pads.
The substrate has the primary coefficient of the thermal expansion. The sealing cap has the secondary coefficient of thermal expansion. When the primary coefficient of the thermal expansion is extremely different from the secondary coefficient of the thermal expansion, a shearing stress is caused to occur in the conductor bumps by heating and cooling the chip, the substrate, and the sealing cap. Consequently, the semiconductor device is easily destroyed by the shearing stress.